One common and ongoing problem faced by the electronics industry is the protection of circuit components against electrostatic discharge (ESD). Generally, ESD is the transfer of an electrostatic charge between bodies at different electrostatic potentials or voltages, caused by direct contact or induced by an electrostatic field. Integrated circuits, in particular, have become more prone to damage or destruction from ESD as their internal structures and geometric features have become smaller.
The management and prevention of ESD is especially challenging in industrial and automotive environments, where high voltage circuits are common, and where the operation of motors, machinery and other inductive circuits can generate large power-line disturbances. In order to facilitate the design of circuits that can operate in such environments, organizations, such as the International Organization for Standards (ISO), have developed standards outlining the type of electrical environment such circuits should withstand.
One example of such a standards is ISO 10605:2008, entitled, “Road vehicles—Test methods for electrical disturbances from electrostatic discharge.” FIG. 1 illustrates a negative test pulse defined by ISO 10605 that represents a possible power line disturbance caused by inductive switching within the automotive environment. Here, the test pulse starts at a nominal battery voltage UA of about 12V. The test pulse is decreased to zero volts and then transitions from zero volts to between −75V to −100V with a 10% to 90% rise time (tr) of about 1 μs. If applied to a system power supply voltage, this test pulse represents a very rapid change in the polarity and supply voltage of any component coupled to a power supply. In order for a circuit to withstand such a pulse, on-chip and off-chip ESD, clamping and ISO structures are used to protect the circuit.